The architecture of the Java Card standard ЕМV

The Java Card EMV

The Java Card EMV architecture of the standard contactless card uses electromagnetic waves to provide information exchange between the card and the terminal. Interaction between the card and the terminal is based on the protocols described in ISO 14443, ISO 15693, ISO 18000, ISO 18092, ISO 10536, and others. in banking technologies, the IS014443 a&B standard is most often used, which is accepted by the leading payment systems VISA and MasterCard as the base for implementing financial applications of these systems. ISO 14443 a, a subset of ISO 14443, was
it is based on the long-standing and well-known MIFARE product developed by Philips Semiconductors, which is a contactless card with memory.
In accordance with the ISO 14443 standard, data is exchanged between the card and the card reader at a carrier frequency of 13.56 MHz. The distance between the card and the reader should not exceed 10 centimeters. As follows from the ISO 14443 standard, the data exchange rate between the card and the card reader can take values of 106, 212, 424 and 848 Kbit / s and is limited by the card’s energy capabilities. For contactless cards, if there is no internal power source (for example, a battery), the power for the processor built into the card must be extracted from the signal transmitted to the card from the card reader. The power levels used are achieved at a very small distance (a few millimeters) between the card and the card reader. Therefore, today, in most cases, the data exchange rate between the card and the card reader is 106 Kbit/s.
To receive the reader’s signal, a conductor that performs the function of a receiving and transmitting antenna is soldered along the perimeter of the card.
With the exception of the physical mechanism used to exchange information between the card reader and the card, contactless and contact cards are almost identical. (In this book the main attention is focused on contact cards.)
Finally, there are cards that support both contact and contactless interfaces. Previously, all such smart cards contained two chips: contactless and contact. Chip processors could be linked on a card or run autonomously.
The presence of two separate interconnected chips on the card goes against one of the main principles of building a smart card— hiding all the elements of the card’s microcomputer in a single silicon crystal. Therefore, today there are combined cards that are implemented on the basis of a single chip with a single processor and two types of interfaces — contact and contactless. These cards are also called two-interface (dual interface) or combined.
A striking representative of the two-interface card is the jcop30 chip, which implements the implementation of the multi-platform Java Card 2.2.1/Global Platform 2.1.1 operating system performed by IBM. Recently, JC0P40 cards have appeared on the market, adding a USB interface to the standard contact interface defined in ISO 7816 and the contactless interface defined in ISO 14443 A&B.

The chip architecture
A generally accepted approach to the layout of smart card microcomputer components is to place the processor, all types of memory, peripheral modules, and I/o unit in a single-chip chip, rather than in different chips connected by electrical connections.
What is the point of this approach?
In hiding connections between computer elements inside the chip and, consequently, increasing the security of operations performed by the microcomputer and data stored in it.
In providing the specified functionality in a small-size chip.
Combining computer elements in a single chip makes it difficult for an external observer to intercept signals transmitted between individual elements of the chip, since the physical connections between the components of the microcomputer in this case are laid on the surface of a monolithic silicon structure.
If a smart card computer consisted of more than one chip, the connections between the chips would represent obvious places to attack. If the signals transmitted over the connections between the chips are not protected (for example, by encrypting information), they may be intercepted by a third party. This will increase the likelihood of unauthorized retrieval of information from the card.
It is safe to say that the need for secure portable tools that can store information and provide a secure platform for some computing activities was the impetus for the creation of smart cards. Due to the high security of the smart hardware and software platform-
it is often used as a reliable means of authentication and identification of its holder, as well as for performing cryptographic operations in protected mode (Hardware Security Module, or HSM). Protected HSM mode refers to the way the card performs cryptographic operations and stores keys that are physically protected from an external observer. In this case, we are talking about a card application called a security module or Security Application Module (SAM). As a security module, the smart card is used in many systems/devices. Well-known examples of this use of IPC include a cell phone SIM card that performs the function of authenticating the phone owner, an access module, or a cryptographic processor in some models of POS terminals.
The small size of the chip allows you to place it in a plastic card. The chip embedded in a plastic card is exposed to various physical influences when carrying the card, for example in a wallet. The card bends in different directions and can be subjected to unexpected loads. In conventional electronic equipment, in which components are connected to each other by electrical installation, and even in the case of connecting lines on a printed circuit Board, this physical environment is the cause of many malfunctions.
When all elements are Packed in a single chip, loads are applied to all elements equally. Thus, if the chip can be saved as a whole, then its components are likely to be functional. Empirical observations show that if the size of the chip is reduced to about 25 square millimeters (with a nearly square shape of the chip), it can withstand the daily pressures exerted on it by the typical use of credit cards.
Achieving the small size of a chip embedded in a smart card depends on a number of factors:
— the degree of resolution of the technology used to create the chip, which is characterized by the “element size” (for example, the size of one transistor element in the chip), expressed in microns;
types and sizes of memory used;
chip trunk bus widths (8-, 16-, 32 -, and 64-bit buses are used);
the presence of additional elements (such as coprocessors, random number sensors, voltage filters, temperature sensors, memory management modules, etc.) included in the chip to ensure the security of card operations and meet functional requirements.
The chip manufacturing technology has a significant impact on the chip characteristics. This technology determines the size of the transistors on which the chip is built. In 1995, technologies with a design norm of approximately 1 micron were used in mass production of chips. Today, technologies with design standards of 0.25, 0.22 and 0.18 microns are considered progressive.
A number of companies have announced the introduction of design standards of 0.13 microns for the production of chips used in smart cards. When using a technology with this design norm, Infineon managed to place a 32-bit processor, 16 KB RAM, 240 KB ROM, and 912 KB EEPR0M on a chip smaller than 25 square millimeters in its SLE88CFX1M00P product.
In 2006, the company plans to launch a new product with an EEPR0M memory size of up to 20 MB. If this happens, the smart card in future information systems will become a General-purpose computing element that provides high security for the operations it performs.
However, in order for chips to be inexpensive and reliable, chip developers often turn to old and proven technologies instead of using the expensive methods mentioned above. For example, you can optimize the chip size by making the best use of different types of card memory. As shown in Fig.2.5, the size of the chip areas required to create different types of memory differs significantly from each other. It is obvious that in order to optimize the chip size, you need to save on RAM and try to place all static program data (the operating system, which is unchanged throughout the life cycle of the application card)in the most economical ROM memory.

There are also special algorithmic methods for saving RAM. Obviously, using these methods reduces the performance of card applications.
The CPU of the chip can work with no more than a certain amount of RAM (processor address space). The size of the address space is determined by the bit depth of the address bus of the system trunk (the number of lines in the address bus). If the number of lines in the address bus is equal to t, then the amount of addressable memory is equal to 2T bits. Minimizing the size of the chip is also expressed in choosing a smaller number of addressing lines. Most often, 8 – and 16-bit address buses are used, allowing the processor to work with machine words of 256 and 65,536 bits, respectively, at any given time.
The processor is the centerpiece of the smart card chip. It is characterized by bit depth, clock speed, and architecture.
The processor bit depth is the maximum number of bits of information that can be processed simultaneously by the processor. Microprocessor cards use 8 -, 16 -, and 32-bit processors. The speed of operations depends on the processor’s bit depth. The higher the bit depth of the processor, the more information it can process per unit of time, the higher its efficiency. For example, the speed of the multiplication operation in the first approximation is proportional to the square of the processor bit rate, and the speed of the operator
the amount of addition or shift of the register depends on the processor’s bit depth according to the linear law.
Today, 8 – bit and 1B-bit processors are the most widely used in IPCS. 16-bit RISC processors are widely used in multi-layer cards, especially in Java cards. There is a supply and demand on the market for 32-bit processors, which will probably become the norm in a few years. This improvement in capabilities, combined with increased memory size, will open up a new class of tasks that will be assigned to the smart card as a secure and truly personal computing system.
The operation of the processor (as well as other components of the chip) is synchronized by clock pulses from the master generator. The processor clock speed value is defined as the maximum time that the processor performs an elementary action. The higher the processor clock speed, the higher its performance. Therefore, the clock speed is the most important characteristic of the processor. The clock frequency of processors used in microprocessor cards usually ranges from 1 to 33 MHz. If we talk about record holders, they use higher frequency values. For example, the already mentioned Infineon SLE88CFX1M00P chip uses 32-bit processors running at a clock frequency of BB MHz.
Using a clock frequency of 30 MHz allows you to increase the speed of execution of machine commands by 6-10 times compared to the first microprocessors that worked from the reader signal with a clock frequency of 3-5 MHz.
The clock frequency generator can be external or internal for the chip. In the first case, the chip receives a clock signal from an external computer via the CLK contact. In the second case, the chip has its own internal clock (clock frequency generator).
The first chips did not have their own clocks. To ensure the operation of the processor and other elements of the chip, as well as the functioning of communication protocols, an external clock signal of the reader was used, fed to the card via the CLK contact. This signal usually had a frequency in the range of 1 to 8 MHz. In practice, two frequencies are widely used —
3.579 545 and 4.9152 MHz. The frequency values are related, firstly, to the cheapness of the crystals that generate such frequencies, and, secondly, to the fact that these frequencies have integer frequency dividers (372 and 512, respectively), in order to get the data transfer rate of 9600 bits/s that is common in card communications.
Cheapness of crystals was determined by their wide use in industry. For example, crystals with a frequency of 3.57 9545 MHz are used to transmit the color subcarrier frequency in the American television standard NTSC. It is for this reason that the majority of terminals had readers who use the mentioned frequency.
On the other hand, low external clock frequencies have become a bottleneck for improving chip performance over time. Upgrading an extensive fleet of terminals to replace readers that provide higher clock speeds was a difficult and expensive undertaking. The solution to the problem was to use the chip’s own clock or use special hardware and software tools of the chip to increase the clock frequency of the external generator by an integer number of times (2-4 times). Most often, in modern chips, the processor and other components of the chip function with the clock frequency of the internal clock of the chip, and the input clock signal is used only for organizing communication between the card and the terminal.
The architecture of the IPC processor is mainly determined by the system of commands used and the addressing methods. Microprocessor cards use processors with RISC architecture that support a reduced instruction Set Computer (RISC). This set consists of 20-40 commands, which include arithmetic operations, logical commands, address operations, data forwarding commands, I / o commands, control commands, etc.the command System is simplified and reduced to the point that each command is executed in one clock cycle. This approach allows you to improve the performance of the processor.
Today, the Motorola 6805 and Intel 8051 instruction sets are typical for many processors. These instruction sets usually have an extension consisting of memory and register operations, support for addressing modes and I / o operations, and commands used exclusively in smart cards.
The largest manufacturers of smart card microprocessors are Infineon Technologies AG, Renesas Technology (a joint venture between Hitachi and Mitsubishi), STMicroelectronics, Philips, Motorola, NEC, and Atmel Samsung Electronics.
In microprocessor cards, symmetric and asymmetric cryptographic algorithms are used to ensure the integrity and confidentiality of transmitted data, to authenticate the source of information, and to calculate cryptograms (signatures of data consisting of card, terminal, and transaction details). V). In the vast majority of cases, the symmetric encryption algorithm uses the Triple DES (or 3DES) block algorithm, which has a key length of 112 bits and encrypts blocks of 64 bits. The asymmetric encryption algorithm uses the RSA algorithm with a public key module that varies between 1024 and 1984 bits.
The symmetric encryption algorithm is based on the use of permutations, substitutions, compression, and nonlinear table transformations of individual elements of encrypted data blocks (see ADJ. V). These are simple operations that can be implemented in a reasonable amount of time using the standard instruction set of a normal card processor. For example, encrypting a 64-bit block using the DES algorithm (used three times in the 3DES algorithm) on an 8-bit processor with a clock frequency of 3.57 MHz takes about 10 milliseconds and requires about 1 KB of ROM memory to store the program that implements DES and related data (lookup tables and S-transformations). The same encryption operation on a 32-bit processor with a clock frequency of about 30 MHz takes about 100 microseconds.
In chips, special processors called cryptographic coprocessors or cryptoprocessors are used to improve the efficiency of performing cryptographic operations. Cryptoprocessors are designed to perform a reduced set of special operations used in cryptographic algorithms. In the case of a cryptoprocessor to implement the 3DES algorithm, such operations are the permutations, substitutions, compressions, and table transformations already mentioned. By supporting a reduced set of operations, the execution time of cryptographic algorithms on the cryptoprocessor is reduced.

For example, the DES algorithm takes 10 microseconds to implement, which is about 1000 times faster than on an 8-bit CPU and 10 times faster than on a 32-bit CPU.
Given that the total transaction processing time should be 1-3 seconds, it follows from the above that in modern chips it is quite acceptable to use the software implementation of the 3DES algorithm in the chip’s Central processor.
The situation changes radically in the case of the RSA algorithm. It is known that the implementation of an asymmetric encryption algorithm takes approximately 100 times longer than a symmetric one of the same cryptographic strength. The RSA algorithm actively uses block multiplication of two large numbers modulo a large number. This operation requires the presence of non-standard block multiplication commands in the processor’s command system and reducing the resulting result by a multiple of some large fixed number. Without such special commands, the “standard” 8-bit chip processor will execute the RSA algorithm when using the 1024-bit public key module for 10-20 seconds. Taking into account that the total transaction processing time should not exceed 3 seconds, the option of using the main processor of the chip for implementing RSA is not allowed.
As a result, a cryptographic coprocessor is used to perform encryption on a closed (long) key in tens of milliseconds and on an open (short) key in a few milliseconds. Generating an RSA key pair takes less than 10 seconds. These data are typical for calculations with a 1024-bit public key module.
In table. 2.1 the values of the encryption time on the private and public keys of the RSA algorithm with the length of the public key module 1024 bits for some Infineon chips are presented.